1. Field of Invention
This invention relates to digital-to-analog converters compatible with standard single-ended metal-oxide-semiconductor (MOS) technology. More particularly, the invention relates to a mono-polar digital-to-analog converter using a ladder resistor network of equal value diffused resistors in a bipolar circuit. Two types of ladder resistor networks have been employed in digital-to-analog and analog-to-digital converter devices. Metal-oxide-semiconductor (MOS) technology was first applied to hybrid analog-to-digital devices using an R-2R ladder in the voltage-switching mode wherein C-MOS switches were employed to drive a high-impedance ladder network. More recently, MOS technology has been employed to construct monolithic analog-to-digital and digital-to-analog converters wherein a multi-tap, diffused-resistor string, or ladder, is utilized between a reference voltage (V.sub.ref) and ground. A tap was provided for each of the 2.sup.N possible analog voltage levels on the ladder. The ladder was therefore nominated the 2.sup.N R potentiometric technique.
Known n-MOS and p-MOS resistor ladder digital-to-analog converters employ a large number of switches in a so-called tree decoder to reduce the number of drive lines needed. For example, an 8-bit converter generally requires 256 resistors and 510 analog decoder switches. Twice as many resistors and transistors are required to increase resolution by a single bit. In addition, the resistor ladder and tree decoder switches typically occupy the majority of the total die area of a monolithic digital-to-analog converter device.
Improved techniques are needed for reducing the relatively large size of a monolithic MOS converter, for removing the constraints on power supply levels to obtain a bipolar output, and for increasing the resolution of the converter without substantially increasing the element count.
In a MOS device, the voltage of the substrate must be biased to the most negative supply (for n-channel) or most positive supply (for p-channel), which is determined by the logic power supplies. The analog voltages, normally used for conversion references, must be maintained at a level placing a reverse bias between the references and the substrate. Consequently, the relationship between the reference supplies and the logic supply is constrained such that only reverse bias analog power supplies can be used in connection with a single-ended chip power supply.
It is particularly desirable to reduce the number of resistors required in a resistor ladder, because the on-chip resistance increases substantially as the number of resistors is increased. Oscillation problems can occur at high resistance levels. Hysteresis cannot be used to prevent oscillations because the system comparator must be operated at a precise trip point when the digital-to-analog circuit is used as an analog-to-digital converter. High resistance levels therefore are preferably to be avoided.
2. Description of the Prior Art
Monolithic MOS analog-to-digital converters employing resistor ladders include the National Semiconductor Series ADCO800, including the ADCO816 8-bit C-MOS converter. Another exemplary converter is that used in the Intel 8022 single-chip microprocessor.
Prior art MOS converter techniques are described in the following publications:
Hamade, "A Single Chip All-MOS 8-bit A/D Converter", IEEE Journal of Solid-State Electronics, Vol. SC-13 No. 6, Dec. 1978, p. 785. PA0 Check et al., "Microcontroller Includes A-D Converter for Lowest-Cost Analog Interfacing", Electronics, May 25, 1978, p. 122. PA0 Redfern et al., "MOS Sampled-Data Technique Shrinks A-D Chip", Electronics, Sept., 13, 1979, p. 134.